diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
index 68978a0..6f786b9 100644
--- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -57,6 +57,10 @@
 	u-boot,dm-spl;
 };
 
+&pinctrl_i2c1_gpio {
+	u-boot,dm-spl;
+};
+
 &gsc {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts
index 39b0306..d092990 100644
--- a/arch/arm/dts/imx8mm-venice.dts
+++ b/arch/arm/dts/imx8mm-venice.dts
@@ -23,8 +23,11 @@
 
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	gsc: gsc@20 {
@@ -89,6 +92,13 @@
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
+		>;
+	};
+
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index aea48f2..4af6b8b 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -49,6 +49,10 @@
 	u-boot,dm-spl;
 };
 
+&pinctrl_i2c1_gpio {
+	u-boot,dm-spl;
+};
+
 &gsc {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts
index eeae225..9e31b37 100644
--- a/arch/arm/dts/imx8mn-venice.dts
+++ b/arch/arm/dts/imx8mn-venice.dts
@@ -23,8 +23,11 @@
 
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	gsc: gsc@20 {
@@ -89,6 +92,13 @@
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
+			MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
+		>;
+	};
+
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
 			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
index 96b9fa8..f9068eb 100644
--- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
@@ -57,6 +57,10 @@
 	u-boot,dm-spl;
 };
 
+&pinctrl_i2c1_gpio {
+	u-boot,dm-spl;
+};
+
 &gsc {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts
index 6b1a7f1..77e5ac4 100644
--- a/arch/arm/dts/imx8mp-venice.dts
+++ b/arch/arm/dts/imx8mp-venice.dts
@@ -23,8 +23,11 @@
 
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	gsc: gsc@20 {
@@ -89,6 +92,13 @@
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c3
+		>;
+	};
+
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3